Peak detectors are used in many applications to determine the peak level (negative or positive) of an analog signal over some specified period. A digital representation of the detected peak level, obtained via an analog-to-digital converter (ADC), is useful for further signal processing or control purposes. Conventional peak detectors typically detect the peak voltage level via a sample-and-hold process over the sample period, followed by use of an ADC that converts the detected peak voltage level to a corresponding digital code. Flash-type ADCs are frequently used as the ADC in this conversion process. A conventional flash ADC utilizes a parallel bank of comparators to generate a corresponding thermometer code, which is then decoded to generate a corresponding digital output value. However, the conventional utilization of these parallel comparators in the flash ADC can result in excessive power consumption. The sample-and-hold circuit of a peak detector likewise consumes substantial power, as well as requiring considerable circuit layout space. Accordingly, an improved method for peak voltage detection and digitization of the detected peak voltage would be advantageous.